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HD66108
(RAM-Provided 165-Channel LCD Driver for Liquid Crystal Dot Matrix Graphics)
Description
The HD66108T under control of an 8-bit MPU can drive a dot matrix graphic LCD (liquid-crystal display) employing bit-mapped display with support of an 8-bit MPU. Use of the HD66108T enables a simple LCD system to be configured with only a small number of chips, since it has all the functions required for driving the display. The HD66108T also enables highly-flexible display selection due to the bit-mapped method, in which one bit of data in a display RAM turns one dot of an LCD panel on or off. A single HD66108T can display a maximum of 100 x 65 dots by using its on-chip 165 x 65-bit RAM. Also, by using several HD66108T's, a display can be further expanded. The HD66108T employs the CMOS process and TCP package. Thus, if used together with an MPU, it can provide the means for a battery-driven pocket-size graphic display device utilizing the low current consumption of LCDs.
Features
* Four types of LCD driving circuit configurations can be selected:
Configuration Type Column outputs only Row outputs from the left and right sides Row outputs from the right side 1 Row outputs from the right side 2 No. of Column Outputs 165 100 100 132 No. of Row Outputs 0 65 (from left: 32, from right: 33) 65 33
954
HD66108
* Seven types of multiplexing duty ratios can be selected: 1/32, 1/34, 1/36, 1/48, 1/50, 1/64, 1/66 Notes: The maximum number of row outputs is 65. * Built-in bit-mapped display RAM: 10 kbits (165 x 65 bits) * The word length of display data can be selected according to the character font: 8-bit or 6-bit * A standby operation is available * The display can be extended through a multi-chip operation * A built-in CR oscillator * An 80-system CPU interface: o = 4 MHz * Power supply voltage for operation: 2.7V to 6.0V * LCD driving voltage: 6.0V to 15.0V * Low current consumption: 400 A max (at fOSC = 500 kHz, fOSC is external clock frequency) * Package: 208-pin TCP (Tape-Carrier-Package)
Ordering Information
Type No. HD66108T00 HD66108TA0 HD66108TB0 HCD66108BP Package 208 pin TCP (Quad) (Double side) (Double side & folding TCP) (Chip with bump)
Note: The details of TCP pattern are shown in "The Information of TCP."
HD66108 Pad Arrangement
115 pin 51 pin
(DMY22) 116 pin
(DMY24) 50 pin
TYPE CODE
Chip size (X x Y) Coordinate Origin Pad size (X x Y)
: : : :
8.30 x 6.02 mm Pad Center Chip Center 70 x 70 m2 (Bump size)
Y
165 pin (DMY21)
1 pin (DMY23)
(DMY5) (DMY12) 166 pin
X
208 pin (DMY13) (DMY20)
955
HD66108
HD66108 Pad Location Coordinates
Pin Pad No. Name (DMY23) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 X32 Coordinate X 4040 4040 Y -2550 -2450 -2350 -2250 -2150 -2050 -1950 -1850 -1750 -1650 -1550 -1450 -1350 -1250 -1150 -1050 -950 -850 -750 -650 -550 -450 -350 -250 -150 -50 50 150 250 350 450 550 650 750 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Pin Pad No. Name 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 X33 X34 X35 X36 X37 X38 X39 X40 X41 X42 X43 X44 X45 X46 X47 X48 X49 (DMY24) X50 X51 X52 X53 X54 X55 X56 X57 X58 X59 X60 X61 X62 X63 X64 X65 Coordinate X 4040 4040 3700 3600 3500 3400 3300 2700 2600 2500 2400 2300 2200 2100 2000 1900 1800 1700 Y 850 950 1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250 2350 2450 2550 2900 2900 Pin Pad No. Name 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Y66 X67 X68 X69 X70 X71 X72 X73 X74 X75 X76 X77 X78 X79 X80 X81 X82 X83 X84 X85 X86 X87 X88 X89 X90 X91 X92 X93 X94 X95 X96 X97 X98 Coordinate X 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 -100 -200 -300 -400 -500 -600 -700 -800 -900 -1000 -1100 -1200 -1300 -1400 -1500 -1600 Y 2900 Pin Pad No. Name 101 X100 102 X101 103 X102 104 X103 105 X104 106 X105 107 X106 108 X107 109 X108 110 X109 111 X110 112 X111 113 X112 114 X113 115 X114 (DMY24) 116 X115 117 X116 118 X117 119 X118 120 X119 121 X120 122 X121 123 X122 124 X123 125 X124 126 X125 127 X126 128 X127 129 X128 130 X129 131 X130 132 X131 133 X132 Coordinate X Y
-1800 2900 -1900 -2000 -2100 -2200 -2300 -2400 -2500 -2600 -2700 -3300 -3400 -3500 -3600
-3700 2900 -4040 2550 2450 2350 2250 2150 2050 1950 1850 1750 1650 1550 1450 1350 1250 1150 1050 950 850 750
100 X99
-1700 2900
Note: The pin marked by * must be hold VCC.
956
HD66108
Pin No. 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 Pad Name X133 X134 X135 X136 X137 X138 X139 X140 X141 X142 X143 X144 X145 X146 X147 X148 X149 X150 X151 X152 X153 X154 X155 X156 X157 X158 X159 X160 X161 X162 X163 X164 (DMY21) * (DMY5) Coordinate X -4040 Y 650 550 450 350 250 150 50 -50 -150 -250 -350 -450 -550 -650 -750 -850 -950 -1050 -1150 -1250 -1350 -1450 -1550 -1650 -1750 -1850 -1950 -2050 -2150 -2250 -2350 -2450 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 Pin No. * * * * * * * 166 167 168 169 170 171 172 173 174 Pad Name (DMY6) (DMY7) (DMY8) (DMY9) (DMY10) (DMY11) (DMY12) VEE2 VGR VML3 VML2 VMH2 VMH3 VIR VCC4 VCC3 (VCCA) DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Coordinate X -3650 -3550 -3450 -3350 -3250 -3150 -3050 -2920 -2820 -2720 -2620 -2520 -2420 -2320 -2210 -2110 -2010 -1860 -1660 -1460 -1260 -1060 -860 -660 -460 -285 -155 -25 105 250 440 580 755 900 Y -2900 -2900 -2872 -2872 -2850 - -2850 198 199 200 201 202 203 204 205 206 207 208 * * * * * * * * Pin No. 192 193 194 195 196 197 Pad Name Coordinate X 1030 1160 1290 1400 1500 1600 1700 1815 1995 2105 2205 2320 2420 2520 2620 2720 2820 2920 3050 3150 3250 3350 3450 3550 3650 3750 Y -2850 -2850 -2882 -2882 -2900 -2900 (Unit : m)
5(6(7
TEST2 TEST1 BND3 GND2 GND1 (GNDA) OSC2 OSC1 VCC2 VCC1 VIL VMH1 V3 V4 VML1 V6L VEE1 (DMY13) (DMY14) (DMY15) (DMY16) (DMY17) (DMY18) (DMY19) (DMY20)
5' :5
RS
&6
M FLM CL1 CO MS
-4040 -2550 -3750 -2900
Note: The pin marked by * must be hold VCC.
957
958
X152 56 X116 92
HD66108
Pin Arrangement
Note : These figures of TCP are not drawn to a scale.
44 X164 93
X115
HD66108T00 (Top View)
HD66108TA0 HD66108TB0 (Top View)
VEE2 V6R VML3 VML2 VMH2 VMH3 V1R VCC4 VCC3 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 RD WR RS CS M FLM CL1 CO M/S RESET TEST2 TEST1 GND3 GND2 GND1 OSC2 OSC1 VCC2 VCC1 V1L VMH1 V3 V4 VML1 V6L VEE1 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
208
X0
X153 X154 X155 X156 X157 X158 X159 X160 X161 X162 X163 X164 VEE2 V6R VML3 VML2 VMH2 VMH3 V1R VCC4 VCC3 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 RD WR RS CS M FLM CL1 CO M/S RESET TEST2 TEST1 GND3 GND2 GND1 OSC2 OSC1 VCC2 VCC1 V1L VMH1 V3 V4 VML1 V6L VEE1 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 208 207 206 205 204 203 202 201 200 199 198 197 159 196 X12 160 X48
X49
HD66108
Pin Description
Classification No. of Pins Symbol Power supply 8, 9, 35, 36 12 to 14 1, 43 VCC1-VCC4 GND1-GND3 VEE1, VEE2 I/O No.of Pins -- -- -- 4 3 2 Function Connect these pins to VCC. Ground these pins. These pins supply power to the LCD driving circuits and should usually be set to the V6 level. Apply an LCD driving voltage V1 to V6 to these pins.
2, 7 37, 42 4, 5 6, 39, 38 3, 40, 41 CPU interface 23
V6L, V1L, -- V1R, V6R, V4, V3, VMH1-VMH3, VML1-VML3
&6
12
I
1
Input a chip select signal via this pin. A CPU can access the HD66108T's internal registers only while the &6 signal is low. Input a write enable signal via this pin. Input a read enable signal via this pin. Input a register select signal via this pin. Data is transferred between the HD66108T and a CPU via these pins. These pins output LCD driving signals. The X0-X31 and X100-X164 pins are column/row common pins and output row driving signals when so programmed. X32-X99 pins are column pins. This pin outputs a first line marker when the HD66108T is a master chip and inputs the signal when the chip is a slave chip. This pin outputs latch clock pulses of display data when the chip is a master chip and inputs clock CL1 pulses when the chip is a slave chip. This pin outputs or inputs an M signal, which converts LCD driving outputs to AC; it outputs the signal when the HD66108T is a master chip and inputs the signal when the chip is a slave chip.
25 26 24 27 to 34 LCD driving output 44 to 208
:5 5'
I I I
1 1 1
RS DB7-DB0 X164-X0
I/O 8 O 165
LCD interface
21
FLM
I/O 1
20
CL1
I/O 1
22
M
I/O 1
959
HD66108
Classification Control signals No.of Pins 10 11 19 Symbol OSC1 OSC2 CO I/O I O O No.of Pins 1 1 1 Function Input system clock pulses via this pin. This pin outputs clock pulses generated by the internal CR oscillator. This pin outputs the same clock pulses as the system clock pulses. Connect with the OSC1 pin of a slave chip. This pin specifies master/slave. Set this pin low when the HD66108T is a master chip and set high when the chip is a slave chip; must not be changed after power-on. Input a reset signal via this pin. Setting this pin low initializes the HD66108T. These pins input a test signal and must be set low.
18
0/S
I
1
17 15, 16
5(6(7
I I
1 2
TEST1, TEST2
960
HD66108
Internal Block Diagram
VML1 VMH1 VEE1 V6L V4 V3 V1L VCC1 X0 X31 X32 X99 X100 X164 VMH3 VML3 V6R VCC4 V1R VMH2 VHL2 VEE2
Row/column driver
Column driver Level shifter
Row/column driver
Data latch circuit 2
X decoder
165 x 65-bit display memory
7 MPX
Row counter
Y address counter
Y decoder 3 VCC2-VCC3 GND1-GND3 X address counter 5 2
Memory I/O buffer
8- to 6-bit converter
X address register Y address register M CL1 FLM M/S Timing generator Control register Mode register C select register RESET CO OSC2 OSC1 TEST1 TEST2 I/O controller I/O buffer
Clock pulse frequency divider
MPX BUSY MPX
Address register
CS WR RD RS
DB7-DB0
961
HD66108
Register List
Reg. Register Read/ CS RS 2 1 0 Symbol Name Write 7 1 -- -------- Invalid -- Reg. No. Data Bit Assignment 6 5 4 3 2 1 0 Busy Time -- Notes 1
0
0
-- -- -- AR
Address R W
Busy STBY DISP
Register No.
None
0
1
0 0 0 DRAM
Display memory X address Y address Control
R W R W R W R W
D7
D6
D5
D4
D3
D2
D1
D0
8 clocks max
2 3
0
1
0 0 1 XAR
XAD
None 1.5 clocks max
0
1
0 1 0 YAR
YAD
None 1.5 clocks max
0
1
0 1 1 FCR
INC
WLS PON
ROS
DUTY
None
0
1
1 0 0 MDR
Mode
R W
FFS
DWS
None
0
1
1 0 1 CSR
C select R W
EOR
CLN
None
0
1
110--
Invalid
--
--
0
1
111--
Invalid
--
--
Notes: 1. Shaded bits are invalid. Writing 1 or 0 to invalid bits does not affect LSI operation. Reading these bits returns 0. 2. DRAM is not actually a register but can be handled as one. 3. Setting the WLS bit of control register to 1 invalidates D7 and D6 bits of the display memory register. 4. DRAM must not be written to or read from until a time period of tCL1 has elapsed rewriting the DUTY bit of FCR or the FFS bit of MDR. tCL1 can be obtained from the following equation; in general, a time period of 1 ms or greater is sufficient if the frame frequency is 60-90 Hz.
tCL1 = D2 (ms) ................ Equation Ni*fCLK(kHz)
D2 (duty correction value): 192 (duty = 1/32, 1/34, or 1/36) 128 (duty = 1/48 or 1/50) 96 (duty = 1/64 or 1/66) Ni (frequency-division ratio specified by the mode register's FFS bits): 2, 1, 1/2, 1/3, 1/4, 1/6, or 1/8 Refer to "6. Clock and Frame Frequency." fCLK: Input clock frequency (kHz)
962
HD66108
System Description
The HD66108T can assign a maximum of 65 out of 165 channels to row outputs for LCD driving. It also incorporates a timing generator and display memory, which are necessary to drive an LCD. If connected to an MPU and supplied with LCD driving voltage, one HD66108T chip can be used to configure an LCD system with a 100 x 65 dot panel (Figure 1). In this case, clock pulses should be supplied by the internal CR oscillator or the MPU. Using LCD expansion signals CL1, FLM and M enables the display size to be expanded. In this case, LCD expansion signal pins output corresponding signals when pin /S is set low for master mode and conversely input corresponding signals when pin /S is set high for slave mode; LCD expansion signal pins of both master chip and slave chips must be mutually connected. Figure 2 shows a basic system configuration using two HD66108T chips.
100 x 65-dot LCD
65-row output
Control bus
100-column output
MPU Data bus
HD66108T
LCD driving power supply
Figure 1 Basic System Configuration (1)
963
HD66108
265 x 65-dot LCD
65-row output
Control bus
165-column output
100-column output
MPU Data bus
HD66108T (Master chip)
HD66108T (Slave chip)
LCD expansion signals LCD driving power supply
Figure 2 Basic System Configuration (2)
964
HD66108
Functional Description
1. Display Size Programming A variety of display sizes can be programmed by changing the system configuration and internal register settings. (1) System Configuration Using One HD66108T Chip When the 65-row-output mode is selected by internal register settings, a maximum of 100 dots in the X direction can be displayed (Figure 3 (a)). Display size in the Y direction can be selected from 32, 34, 36, 48, 50, 64, and 65 dots according to display duty setting. Note that Y direction settings does not affect those in the X direction (100 dots). When the 33-row-output mode is selected by internal register settings, a maximum of 132 dots in the X direction can be displayed (Figure 3 (b)). Table 1 shows the relationship between display sizes and the control register's (FCR) ROS and DUTY bits. ROS and DUTY bit settings determine the function of X pins. For more details, refer to "4.1 Row Output Pin Selection." (2) System Configuration Using One HD66108T Chip and One HD61203 Chip as Row Driver A maximum of 64 dots in the Y direction and 165 dots in the X direction can be displayed. 48 or 64 dots in the Y direction can be selected by HD61203 pin settings (Figure 3 (c)). (3) System Configuration Using Two or more HD66108T Chips X direction size can be expanded by 165 dots per chip. Figure 3 (d) shows a 265 x 65-dot display. Y direction size can be expanded up to 130 dots with 2 chips; a 100 x 130-dot display provided by 2 chips is shown in Figure 3 (e). Table 1 Relationship between Display Size and Register Settings (No. of Dots)
Duty Bit Setting (Multiplexing Duty Ratio) 1/32 1/34 1/36 1/48 1/50 1/64 1/66
ROS Bit Setting (X0-X164 Pin Function) 165-column-output
Specified by a row driver X: 100 Y: 34 X: 100 Y: 34 X: 132 Y: 33 X:100 Y: 36 X:100 Y: 36 X: 132 Y: 33 X: 100 Y: 48 X: 100 Y: 48 X: 132 Y: 33 X: 100 Y: 50 X: 100 Y: 50 X: 132 Y: 33 X: 100 Y: 64 X: 100 Y: 64 X: 132 Y: 33 X:100 Y: 65 X:100 Y: 65 X: 132 Y: 33
65-row-output from the right side X: 100 Y: 32 65-row-output from the left and right sides X: 100 Y: 32
33-row-output from the right side X: 132 Y: 32
965
HD66108
X: 100 dots X: 132 dots Y: 33 dots Y: 65 dots (b) Configuration Using One HD66108T Chip (2) (33-Row Output from the Right Side) (a) Configuration Using One HD66108T Chip (1) (65-Row Output from the Right Side) X: 165 dots
Y: 64 dots
(c) Configuration Using One HD66108T Chip and One HD61203 as Row Driver (165-Column Output) X: 265 dots
Area displayed by chip 1
Area displayed by chip 2
Y: 65 dots
(d) Configuration Using Two HD66108T Chips (1) X: 100 dots
Area displayed by chip 1
Y: 130 dots
Area displayed by chip 2
(e) Configuration Using Two HD66108T Chips (2)
Figure 3 Relationship between System Configurations and Display Sizes
966
HD66108
2. Display Memory Construction and Word Length Setting The HD66108T has a bit-mapped display memory of 165 x 65 bits. As shown in Figure 4, data from the MPU is stored in the display memory, with the MSB (most significant bit) on the left and the LSB (least significant bit) on the right. The sections on the LCD panel corresponding to the display memory bits in which 1's are written will be displayed as on (black). Display area size of the internal RAM is determined by control register (FCR) settings (refer to Table 1). The start address in the Y direction for the display area is always Y0, independent of the register setting. In contrast, the start address in the X direction is X0 in the modes for 165-column-output, 65-row-output from the right side, and 33-row-output from the right side, and is X32 in the 65-row-output mode from the left and right sides. Each display area contains the number of dots shown in Table 1, beginning from each start address. For more detail, refer to "4.2 Row Output Data Setting," Figures 15 to 19. In the display memory, one X address is assigned to each word of 8 or 6 bits long in X direction. (Either 8 or 6 bits can be selected as word length of display data.) Similarly, one Y address is assigned to each row in Y direction. Accordingly, X address 20 in the case of 8-bit word and X address 27 in the case of 6-bit word have 5 and 3 bits of display data, respectively. Nevertheless, data is also stored here with the MSB on the left (Figure 5).
Display on COM1 COM2 165 x 65-dot LCD
COM65
X0 X1 X2 X3 X4 X5 X6 X7 X164
Y0
1
0
1
0
0
1
0
1 DB0 (LSB)
Y direction
DB7 (MSB)
156 x 65-bit display memory
Y64
Figure 4 Relationship between Memory Construction and Display
967
HD66108
(H'00) (H'01) (H'02) 0 1 2 0(H'00) 1(H'01) 8 bit (H'12) 18 X address (H'13) (H'14) 19 20
63(H'3F) 64(H'40) Y address (a) Address Assignment When 1 Word Is 8 Bits Long X address (H'18)(H'19)(H'1A)(H'1B) 24 25 27 26
(H'00)(H'01)(H'02)(H'03) 2 0 1 3 0(H'00) 1(H'01) 6 bit
63(H'3F) 64(H'40) Y address
(b) Address Assignment When 1 Word Is 6 Bits Long
Figure 5 Display Memory Addresses
968
HD66108
3. Display Data Write 3.1 Display Memory and Data Register Accesses (1) Access Figure 6 shows the relationship between the address register (AR) and internal registers and display memory in the HD66108T. Display memory shall be referred to as a data register since it can be handled as other registers. To access a data register, the register address assigned to the desired register must be written into the address register's Register No. bits. The MPU will access only that register until the register address is updated.
Registers accessible with pin RS = 0 Address register Bit 7 6 5 4 3 2 1 Register No. 0
Registers accessible with pin RS = 1 Data registers
Register No. =0 Display memory
=1 X address register
=2 Y address register
=3 Control register
=4 Mode register
=5 C select register
Figure 6 Relationship between Address Register and Register No.
969
HD66108
(2) Busy Check A busy time period appears after display memory read/write or X or Y address register write, since post-access processing is performed synchronously with internal clock pulses. Updating data in registers other than the address register is disabled during this time. Subsequent data must be input after confirming ready mode by reading the address register. The busy time period is a maximum of 8 clock pulses after display memory read/write and a maximum of 1.5 clock pulses after X or Y address register write (Figure 7).
HD66108T OSC
BUSY FLAG Ready Internal operation Operates internally CPU WR Busy 8 clock pulses max Ready
RD
RS
DB7
Figure 7 Relationship between Clock Pulses and Busy Time (Updating Display Data)
970
CS RS WR RD
BUSY CHECK AR WRITE XAR WRITE BUSY CHECK AR WRITE YAR WRITE BUSY CHECK AR WRITE DRAM READ BUSY CHECK DRAM READ BUSY CHECK DRAM READ
Sets an X address Xm (address increment direction: X)
Sets a Y address Yn
Display memory dummy read *
(Xm, Yn) (Xm+1, Yn) (Xm+2, Yn)
DB (accessed register) Output data
(3) Dummy Read When reading out display data, the data which is read out immediately after setting the X and Y addresses is invalid. Valid data can be read out after one dummy read, which is performed after setting the X and Y addresses desired (Figure 8).
Figure 8 Display Memory Reading
X and Y addresses
(Xm, *) (Xm, Yn) (Xm+1, Yn)
(Xm+2, Yn)
HD66108
971
HD66108
(4) Limitations on Access As shown in Figure 9, the display memory must not be rewritten until a time period of tCL1 or longer has elapsed after rewriting the control register's DUTY bits or the mode register's FFS bits. However, display memory and registers other than the control register and mode register can be accessed even during this time period. tCL1 can be obtained from the following equation. If using an LSI with a frame frequency of 60 Hz or greater, a time period of 1 ms should be sufficient.
tCL1= D2 (ms) ...... Equation 1 Ni*fCLK(kHz)
D2 (duty correction value): 192 (duty = 1/32, 1/34, or 1/36) 128 (duty = 1/48 or 1/50) 96 (duty = 1/64 or 1/66) Ni (frequency-division ratio specified by the mode register's FFS bits): 2, 1, 1/2, 1/3, 1/4, 1/6, or 1/8 fCLK: Input clock frequency (kHz) 3.2 X and Y address Counter Auto-Incrementing Function As described in "2. Display Memory Construction and Word Length Setting," the HD66108T display memory has X and Y addresses. Internal X address counter and Y address counter both employ an autoincrementing function. After display data is read or written, the X or Y address is incremented according to the address increment direction selected by internal register. Although X addresses up to 20 are valid when 8 bits make up one word (up to 27 when 6 bits make up one word), the X address counter can count up to 31 since it is a 5-bit free counter. Similarly, although Y addresses up to 64 are valid, the Y address counter can count up to 127. Consequently, X or Y address must be reset at an appropriate point as shown in Figure 10.
Rewriting DUTY or FFS bits
Accessing other registers
tCL1 or longer
Rewriting display memory
Figure 9 Rewriting Display Memory after Rewriting Registers
972
HD66108
X address counted 0 1 2 Set address Write display data Valid addresses
20 21
Reset X address Dummy read/write
Invalid addresses
31 (1) Example of X Address Counter Increment (Word Length: 8 Bits)
Y address counted
0 1 2
Set address Write display data Valid display area
31 32
Reset Y address Dummy read/write
Invalid display area
127 (2) Example of Y Address Counter Increment (Multiplexing Duty Ratio: 1/32)
Figure 10 X/Y Address Counter Increment
973
HD66108
4. Selection for LCD Driving Circuit Configuration 4.1 Row Output Pin Selection The HD66108T can assign a maximum of 65 pins for row outputs among the 165 pins named X0-X164. The X0-X164 pins can be classified into four blocks labelled A, B, C, and D (Figure 11 (a)). Blocks A, C, and D consist of row/column common pins and block B consists of column pins only. The output function of the LCD driving pins and the combination of blocks can be selected by internal registers. Figure 11 shows an example of 165-column-output mode. This configuration is useful when using more than one HD66108T chip or using the HD66108T as a slave chip of the HD61203U. Figure 12 shows an example of 65-row-output mode from the right side. Blocks A and B are used for column output and blocks C and D (X100-X164 pins) for row output. This configuration offers an easy way of connecting row output lines in the case of using one or more HD66108T chips. Figure 13 shows an example of 65-row-output mode from the left and right sides. 32 pins of X0-X31 and 33 pins of X132-X164 are used for row output here. This configuration offers an easy way of connecting row output lines in the case of using only one HD66108T chip. Figure 14 shows an example of 33-row-output mode from the right side. Block D, i.e., X132-X164 pins, is used for row outputs. This configuration provides a means for assigning many pins to column outputs when 1/32 or 1/34 multiplexing duty ratio is desired. In all modes, it is row data and multiplexing duty ratio that determine which pins are actually used among the pins assigned to row output. Y values shown in Table 1 indicate the numbers of pins that are actually used. Pins not used must be left disconnected.
974
HD66108
X32 X0 X31 X99 X100 X131 X132 X164
Column driver Block A
Column driver Block B
Column driver Block C
Column driver Block D
(a) LCD Driving Circuit Configuration
Row driver
LCD
165-column output
HD66108T
(b) System Configuration
Figure 11 165-Column-Output Mode
975
HD66108
X32 X0 X31 X99 X100 X131 X132 X164
Column driver Block A
Column driver Block B
Row driver Block C
Row driver Block D
(a) LCD Driving Circuit Configuration
LCD
65-row output
100-column output
HD66108T
(b) System Configuration
Figure 12 65-Row-Output Mode from the Right Side
976
HD66108
X32 X0 X31 X99 X100 X131 X132 X164
Row driver Block A
Column driver Block B
Column driver Block C
Row driver Block D
(a) LCD Driving Circuit Configuration
32-row output LCD 33-row output
100-column output
HD66108T
(b) System Configuration
Figure 13 65-Row-Output Mode from the Left and Right Sides
977
HD66108
X32 X0 X31 X99 X100 X131 X132 X164
Column driver Block A
Column driver Block B
Column driver Block C
Row driver Block D
(a) LCD Driving Circuit Configuration
LCD
33-row output
132-column output
HD66108T
(b) System Configuration
Figure 14 33-Row-Output-Mode from the Right Side
978
HD66108
4.2 Row Output Data Setting If certain LCD driving output pins are assigned to row output, data must be written to display memory for row output. The specific area to which this data must be written depends on the row-output mode and the procedure of writing row data to the display memory (0 or 1 to which bits?) depends on which X pin drives which line of the LCD. Row data area is determined by the control register's (FCR) ROS and DUTY bits and is identical to the protected area, which will be described below. (165-column-output mode has no protected area, thus requiring no row data to be written (Figure 15).) Procedure of writing row data to the display memory is as follows. First, 1 must be written to the bit at the intersection between line Yj and line (column) Xi (column). Line Yj is filled with data to be displayed on the first line of the LCD and line Xi is connected to pin Xn, which drives the first line of the LCD. Following this, 0s must be written to the remaining bits on line Yj in the row data area. This rule applies to subsequent lines on the LCD. Table 2 shows the relationship between FCR settings and protected areas. Figure 16 shows the relationship between row data and display. Here the mode is 65-row output from the right side. Display data on Y0 is displayed on the first line of the LCD and data on Y64 is displayed on the 65th line of the LCD. If X164 is connected to the first line of the LCD and X100 is connected to the 65th line of the LCD, 1s must be written to the bits on the diagonal line between coordinates (X164, Y0) and (X100, Y64) and 0s to the remaining bits. Row data protect function must be turned off before writing row data and be turned on after writing row data. Turning on the row data protect function disables read/write of display memory area corresponding to the row output pins, i.e., prevents row data from being destroyed. In Figure 16, display memory area corresponding to pins X100 to X164 is protected. Figures 17 to 19 show examples of row data settings. Some multiplexing duty ratios result in invalid display areas. Although an invalid display area can be read from or written to, it will not be displayed. Table 2 Relationship between FCR Settings and Protected Areas
Control Register (FCR) ROS PON 1 1 1 1 4 0 0 1 1 3 0 1 0 1 Mode 165-column 65-row (R) 65-row (L/R) 33-row (R) LCD Driving Signal Output Pins Connected to Protected Area of Display Memory No area protected X100-X164 X0-X31 and X132-X164 X132-X164
Figures 15 16, 19 17 18
65-row (R) : 65-row-output mode from the right side 65-row (L/R): 65-row-output mode from the left and right sides 33-row (R): 33-row-output mode from the right side
979
HD66108
Row driver Control register ROS bit = 00 DUTY bit = 101 LCD driving voltages: VMH1 = V3, VML1 = V4, VMH2 = V3, VML2 = V4, VMH3 = V3, VML3 = V4
165-column driver HD66108T
X0---
---X31 X32---
---X99 X100---
---X131 X132---
---X164
Column driver Block A (32 bits) X address 4 bytes 8 bits/1 word 6 bits/1 word
0 1 2 3 4
Column driver Block B (68 bits)
Column driver Block C (32 bits) 4 bits + 3 bytes + 4 bits
11 12 13 14 15 16
Column driver Block D (33 bits) 4 bits + 3 bytes + 5 bits
17 18 19 20
8 bytes + 4 bits 4 bits + 10 words + 4 bits
5 6 15 16
5 words + 2 bits
0 1 2 3 4
2 bits + 5 words
17 18 19 20 21 22
5 words + 3 bits
23 24 25 26 27
165 x 64-dot LCD
X0 X1
X2 X3
X4
X160
X162
X164
X161
X163
Y0 0 Y1 1 Y2 1 Y3 1 Y4 1
1 0 1 0 0
1 0 1 0 0
0 1 1 1 1
0 0 0 0 0
1 1 1 1 1
1 0 1 0 0
1 0 1 0 0
0 1 0 0 0
0 0 0 0 0
Display data
0 1 0 0 0 0 0 0 0 0 0 1 1 1
Valid display area
Y62 0 Y63 0 Y64
0 1
1 0
Invalid display data
Invalid display area
Figure 15 Relationship between Row Data and Display (165-Column Output, 1/64 Multiplexing Duty Ratio)
980
HD66108
Control register ROS bit = 01 DUTY bit = 110 LCD driving voltages: VMH1 = V3, VML1 = V4, VMH2 = V2, VML2 = V5, VMH3 = V2, VML3 = V5
100-column driver HD66108T 65-row driver
---X164
X0---
---X31 X32---
---X99 X100---
---X131 X132---
Column driver Block A (32 bits) X address 4 bytes 8 bits/1 word 6 bits/1 word
0 1 2 3 4
Column driver Block B (68 bits)
Row driver Block C (32 bits)
Row driver Block D (33 bits)
8 bytes + 4 bits
11 12
Row data protected blocks 4 bits + 3 bytes + 4 bits + 3 bytes + 4 bits 5 bits
13 14 15 16 17 18 19 20
5 words + 2 bits
0 1 2 3 4 5
4 bits + 10 words + 4 bits
6 15 16
2 bits + 5 words
17 18 19 20 21 22
5 words + 3 bits
23 24 25 26 27
100 x 65-dot LCD
X0 X1
X2 X3
X4
X96 X95
X98
X100 X102 X101
X160 X162 X164 X161 X163
X97
X99
Y0 0 1 1 0 0 Y1 1 0 0 1 0 Y2 1 1 1 1 0 Y3 1 0 0 1 0 Y4 1 0 0 1 0
1 1 1 1 1
1 0 1 0 0
1 0 1 0 0
0 1 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 1 0 0 0
1 0 0 0 0
Display memory
Display data
Y62 0 0 1 0 0 Y63 0 1 0 1 0 Y64 1 0 0 0 1 00001001 00011010 00100100
Row data
00000 00000 00000
Accessible area
Area protected with PON = 1
Figure 16 Relationship between Row Data and Display (65-Row Output from the Right Side, 1/66 Multiplexing Duty Ratio)
981
HD66108
Control register ROS bit = 10 DUTY bit = 110 LCD driving voltages: VMH1 = V2, VML1 = V5, VMH2 = V3, VML2 = V4, VMH3 = V2, VML3 = V5 32-row driver
X0-----X31 X32-----X99 X100---
100-column driver HD66108T
---X131 X132---
33-row driver
---X164
Row driver Block A (32 bits) X address 8 bits/1 word 6 bits/1 word
0
Column driver Block B (68 bits) 8 bytes + 4 bits
3 4 11 12
Column driver Block C (32 bits) 4 bits + 3 bytes + 4 bits
13 14 15
Row driver Block D (33 bits)
Row data protected block 4 bits + 3 bytes + 5 bits
16 17 18 19 20
Row data protected block
4 bytes
1 2
5 words + 2 bits
0 1 2 3 4 5
4 bits + 10 words + 4 bits
6 15 16
2 bits + 5 words
17 18 19 20 21 22
5 words + 3 bits
23 24 25 26 27
100 x 65-dot LCD
X0 X1
X30
X32
X34
X36
X128 X130 X132 X127 X129 X131 X133
X164 X163
X31
X33
X35
Y0 1 0 Y1 0 1
0001100 0010010
1110000 1001000
00 00
Row data
Y30 Y31 Y32 Y33 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1
Display data
1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
Row data
Y63 0 0 Y64 0 0 0001010 0010001 0001101 0010010 00 00
Area protected with PON = 1
Accessible area
Area protected with PON = 1
Figure 17 Relationship between Row Data and Display (65-Row Output from the Left and Right Sides, 1/66 Multiplexing Duty Ratio)
982
HD66108
Control register ROS bit = 11 DUTY bit = 001 LCD driving voltages: VMH1 = V3, VML1 = V4, VMH2 = V3, VML2 = V4, VMH3 = V2, VML3 = V5
132-column driver HD66108T 33-row driver
X0---
---X31 X32---
---X99 X100---
---X131 X132---
---X164
Column driver Block A (32 bits) X address 4 bytes 8 bits/1 word 6 bits/1 word
0 1 2 3 4
Column driver Block B (68 bits) 8 bytes + 4 bits
11 12
Column driver Block C (32 bits) 4 bits + 3 bytes + 4 bits
13 14 15
Row driver Block D (33 bits)
Row data protected block 4 bits + 3 bytes + 5 bits
16 17 18 19 20
5 words + 2 bits
0 1 2 3 4 5
4 bits + 10 words + 4 bits
6 15 16
2 bits + 5 words
17 18 19 20 21 22
5 words + 3 bits
23 24 25 26 27
132 x 33-dot LCD
X0 X1
X2 X3
X4
X128 X130 X132 X134 X127 X129 X131 X133
X162 X164 X163
Y0 0 1 1 0 0 Y1 1 0 0 1 0 Y2 1 1 1 1 0
11100000 10010000 11100000
001 010 100
Display data
Y29 0 0 1 0 0 Y31 0 1 0 1 0 Y32 1 0 0 0 1 Y33 0 0 0 0 0 Y34 00001001 00011010 00100100 00000000
Row data
000 000 000 000
Valid display area
Invalid display data
Y63 Y64
Invalid display area
Accessible area
Area protected with PON = 1
Figure 18 Relationship between Row Data and Display (33-Row Output from the Right Side, 1/34 Multiplexing Duty Ratio)
983
HD66108
Control register ROS bit = 01 DUTY bit = 011 LCD driving voltages: VMH1 = V3, VML1 = V4, VMH2 = V2, VML2 = V5, VMH3 = V2, VML3 = V5
100-column driver HC66108T 65-row driver 48-row driver used
---X164
X0---
---X31 X32---
---X99 X100---
---X131 X132---
Column driver Block A (32 bits) X address 4 bytes 8 bits/1 word 6 bits/1 word
0 1 2 3 4
Column driver Block B (68 bits)
Row driver Block C (32 bits)
Row driver Block D (33 bits)
8 bytes + 4 bits
11 12
Row data protected blocks 4 bits + 3 bytes + 4 bits + 3 bytes + 4 bits 5 bits
13 14 15 16 17 18 19 20
5 words + 2 bits
0 1 2 3 4 5
4 bits + 10 words + 4 bits
6 15 16
2 bits + 5 words
17 18 19 20 21 22
5 words + 3 bits
23 24 25 26 27
100 x 48-dot LCD
Unused
X0 X1 X2 X3 X4 X96 X95 X98 X100 X117 X119 X116 X118 X162 X164 X163 X97 X99
Y0 0 1 1 0 0 Y1 1 0 0 1 0 Y2 1 1 1 1 0
111000 100100 111000
0000 0000 0000
001 010 100
Display data
Y45 0 0 1 0 0 Y46 0 1 0 1 0 Y47 1 0 0 0 1 Y48 Y49 000010 000110 001000
Row data Valid row data
0001 0010 0100 000 000 000
Valid display area
Invalid display area
Y63 Y64
Accessible area Note: Pins X100-X116 are left disconnected here.
Area protected with PON = 1
Figure 19 Relationship between Row Data and Display (65-Row Output from the Right Side, 1/48 Multiplexing Duty Ratio)
984
HD66108
4.3 LCD Driving Voltage Setting There are 6 levels of LCD driving voltages ranging from V1 to V6; V1 is the highest and V6 is the lowest. As shown in Figure 20, column output waveform is made up of a combination of V1, V3, V4, and V6 while row output waveform is made up of V1, V2, V5, and V6. This means that V1 and V6 are common to both waveforms while mid-voltages are different. To accommodate this situation, each block of the HD66108T is provided with power supply pins for midvoltages as shown in Figure 21. Each pair of V1R and V1L and V6R and V6L are internally connected and must be applied the same level of voltage. Block B is fixed for column output and must be applied V3 and V4 as mid-voltages. The other blocks must be applied different levels of voltages according to the function of their LCD driving output pins; if the LCD driving output pins are set for row output, VMHn and VMLn must be applied V2 and V5, respectively, while they must be applied V3 and V4, respectively, if the pins are set for column output (n = 1 to 3). Table 3 Relationship between FCR Settings and LCD Driving Voltages
LCD Driving Voltage Pins VIR/VIL V3 V1 V1 V1 V1 V3 V3 V3 V3 V4 V4 V4 V4 V4 VMH1 VML1 VMH2 VML2 VMH3 VML3 V6R/V6L V3 V3 V2 V3 V4 V4 V5 V4 V3 V2 V3 V3 V4 V5 V4 V4 V3 V2 V2 V2 V4 V5 V5 V5 V6 V6 V6 V6
Control Register (FCR) ROS4 ROS3 Mode 0 0 1 1 0 1 0 1 165-column 65-row (R) 65-row (L/R) 33-row (R)
65-row (R): 65-row-output mode from the right side 65-row (L/R): 65-row-output mode from the left and right sides 33-row (R): 33-row-output mode from the right side
985
HD66108
1 V1 V2 V3 V4 V5 V6 Row V1 V2 V3 V4 V5 V6 V1 V2 V3 V4 V5 V6 V1 V2 V3 V4 V5 V6 VLCD 7/9VLCD Columnrow (non selected waveform) 1/9VLCD -1/9VLCD -7/9VLCD -VLCD VLCD 1/9VLCD Columnrow (selected waveform) -1/9VLCD -VLCD 1 frame 2 3 4 1 2 3 4
Column
Figure 20 LCD Driving Voltage Waveforms
986
HD66108
5. Multiplexing Duty Ratio and LCD Driving Waveform Settings A multiplexing duty ratio and LCD driving waveform can be selected via internal registers. A multiplexing duty ratio of 1/32, 1/34, 1/36, 1/48, 1/50, 1/64, or 1/66 can be selected according to the LCD panel used. However, since there are only 65 row-output pins, only 65 lines will be displayed even if 1/66 multiplexing duty ratio is selected. There are three types of LCD driving waveforms, as shown in Figure 22: A-type waveform, B-type waveform, and C-type waveform. The A-type waveform is called per-half-line inversion. Here, the waveforms of M signal and CL1 signal are the same and alternate every LCD line. The B-type waveform is called per-frame inversion; in this case, the M signal inverts its polarity every frame so as to alternate every two LCD frames. This is the most common type. The C-type waveform is called per-n-line inversion and inverts its polarity every n lines (n can be set as needed within 1 to 31 via the internal registers). The C-type waveform combines the advantages of the Aand B-types of waveforms. However, some lines will not be alternated depending on the multiplexing duty ratio and n. To avoid this, another C-type waveform is available which is generated from the EOR of the C-type waveform M signal mentioned above and the B-type waveform M signal. Since the relationship between n and display quality usually depends on the LCD panel, n must be determined by observing actual display results. The B-type waveform should be used if the LCD panel specifies no particular type of waveform. However, in some cases, the C-type waveform may create a better display.
LCD driving output pins X0 X31 X32 X99 X100 X131 X132 X164
Block A
Block B
Block C
Block D
V1L V6L
VMH1 VML1
V3
V4
VMH2 VML2
VMH3 VML3
V6R V1R
LCD driving power supply pins
Figure 21 Relationship between Blocks and LCD Driving Voltages
987
988
1 line A-type waveform (per-half-line inversion) Xn M B-type waveform (per-frame inversion) Xn M 1 frame C-type waveform (per-n-line inversion) Xn EOR function off (n = 5) M
1234512345
HD66108
C-type waveform (per-n-line inversion) Xn EOR function on (n = 5) M
Figure 22 LCD Driving Waveforms (Row Output with a 1/32 Multiplexing Duty Ratio)
HD66108
6. Clock and Frame Frequency An input clock with a 200-kHz to 4-MH frequency can be used for the HD66108T. Note that raising clock frequency increases current consumption although it reduces busy time and enables high-speed operations. An optimum system clock frequency should thus be selected within 200 kHz to 4 MHz. The clock frequency driving the LCD panel (= frame frequency) is usually 70 Hz to 90 Hz. Accordingly, the HD66108T is so designed that the frequency-division ratio of the input clock can be selected. The HD66108T generates around 80-Hz LCD frame frequency if the frequency-division ratio is 1. The frequency-division ratio can be obtained from the following equation.
Ni = fF 500 fCLK x 80 x D1
Ni: fF : fCLK: D1:
Frequency-division ratio Frame frequency required for the LCD panel (Hz) Input clock frequency (kHz) Duty correction value 1 D1 = 1 when multiplexing duty ratio is 1/32, 1/48 or 1/64 D1 = 32/34 when multiplexing duty ratio is 1/34 D1 = 32/36 when multiplexing duty ratio is 1/36 D1 = 48/50 when multiplexing duty ratio is 1/50 D1 = 64/66 when multiplexing duty ratio is 1/66
The frequency-division ratio nearest the value obtained from the above equation must be selected; selectable frequency-division ratios by internal registers are 2, 1, 1/2, 1/3, 1/4, 1/6, and 1/8. 7. Display Off Function The HD66108T has a display off function which turns off display by rewriting the contents of the internal register. This prevents random display at power-on until display memory is initialized.
989
HD66108
8. Standby Function The HD66108T has a standby function providing low-power dissipation. Writing a 1 to bit 6 of the address register starts up the standby function. The LCD driving voltages, ranking from V1 to V6, must be set to VCC to prevent DC voltage from being applied to an LCD panel during standby state. The HD66108T operates as follows in standby mode. (1) Stops oscillation and external clock input (2) Resets all registers to 0's except the STBY bit Here, note that the display memory will not preserve data if the standby function is turned on; the display memory as well as registers must be set again after the standby function is terminated. V1 to V6 terminals must be connected to VCC to prevent DC voltage being supplied during stand by. Table 4 shows the standby status of pins and Table 5 shows the status of registers after standby function termination. Writing a 0 to bit 6 of the address register terminates the standby function. Writing values into the DISP and Register No. bits at this time is ignored; these bits need to be set after the standby function has been completely terminated. Figure 23 shows the flow for start-up and termination of the standby function and related operations.
990
HD66108
Table 4
Pin OSC2 CO CL1 FLM M Xn Xn'
Standby Status of Pins
Status High Low Low (master chip) or high-impedance (slave chip) Low (master chip) or high-impedance (slave chip) Low (master chip) or high-impedance (slave chip) V4 (column output pins) V5 (row output pins)
Table 5
Register Status after Standby Function Termination
Status after Standby Function Termination Reset to 0's except for the STBY bit Reset to 0's Reset to 0's Reset to 0's Reset to 0's Reset to 0's Data not preserved
Register Name Address register X address register Y address register Control register Mode register C select register Display memory
991
HD66108
Start-up Set the LCD driving voltages to VCC level
Set the STBY bit to 1 (turn on the standby function)
Wait until external clock pulses stabilize
*1
Termination
Set the STBY bit to 0 (turn off the standby function)
Supply the LCD driving voltages
Set registers again
Wait for a time period of tCL1 or longer
*2
Set the display memory
Set the DISP bit to 1 (turn on LCD)
Notes: 1. Not necessary in the case of using internal oscillation. 2. Refer to equation 1 (Section 3.1).
Figure 23 Start-Up and Termination of Standby Function and Related Operations
992
HD66108
9. Multi-Chip Operation Using multiple HD66108T chips (= multi-chip operation) provides the means for extending the number of display dots. Note the following items when using the multi-chip operation. (1) The master chip and the slave chips must be determined; the /S pin of the master chip must be set low and the /S pin of the slave chips must be set high. (2) All the HD66108T chips will be slave chips if HD61203 or its equivalent is used as a row driver. (3) The master chip supplies the FLM, CL1, and M signals to the slave chips via the corresponding pins, which synchronizes the slave chips with the master chip. (4) Since a master chip outputs synchronization signals, all data registers must be set. (5) The following bits for slave chips must always be set: INC, WLS, PON, and ROS (control register) FFS (mode register) It is not necessary to set the control register's DUTY bits, the mode register's DWS bits, or the C select register. For other registers' settings, refer to Table 6. (6) All chips must be set to LCD off in order to turn off the display. (7) The standby function of slave chips must be started up first while that of the master chip must be terminated first. Figure 24 to 26 show the connections of the synchronization signals for different system configurations and Table 6 lists the differences between master mode and slave mode. Table 6
Item Pin:
0/S
Comparison between Master and Slave Mode
Master Mode Must be set low Oscillation is possible = OSC1 Output signals Valid Valid Valid Valid Valid Valid (only if the DWS bits are set for the C-type waveform) Slave Mode Must be set high Oscillation is possible = OCS1 Input signals Valid Valid Valid Valid except for the DUTY bits Valid except for the DWS bits Invalid
OSC1, OSC2 CO FLM, CL1, M Register: AR XAR YAR FCR MDR CSR
Notes: Valid: Needs to be set Invalid: Needs not be set
993
HD66108
Row output LCD
Column output
Column output
HD66108T Slave mode
M M
HD66108T Master mode
OSC1 FLM CL1
OSC1 FLM
CL1
Clock Note: Clock pulses for the slave chip can be supplied from the master chip's CO pin.
Figure 24 Configuration Using Two HD66108T Chips (1)
994
HD66108
Row output LCD
Column output
Column output
HD66108T Master mode
M M
HD66108T Slave mode
OSC1 FLM CL1
OSC1 FLM
CL1
Clock Note: Clock pulses for the slave chip can be supplied from the master chip CO pin.
Figure 25 Configuration Using Two HD66108T Chips (2)
995
HD66108
Row output
LCD
Column output
HD61203U Row driver
M M
HD66108T Slave mode
CR FRM CL2
OSC1 FLM
CL1
Clock Notes: 1. The slave chip can oscillate CR clock pulses. In this case, the clock pulses must be supplied to the HD61203U from the HD66108T's CO pin. 2. The HD61203U's control pins must be set in accordance with the type of RAMs.
Figure 26 Configuration Using One HD66108T Chip with Another Row Driver (HD61203U)
996
HD66108
Internal Registers
All HD66108T's registers can be read from and written into. However, the BUSY FLAG and invalid bits cannot be written to and reading invalid bits or registers returns 0's. 1. Address Register (AR) (Accessed with RS = 0) This register (Figure 27) contains Register No. bits, BUSY FLAG bit, STBY bit, and DISP bit. Register No. bits select one of the data registers according to the register number written. The BUSY FLAG bit indicates the internal operation state if read. The STBY bit activates the standby function. The DISP bit turns the display on or off. This register is selected when RS pin is 0. Bits D4 and D3 are invalid.
D7 BUSY FLAG D6 D5 D4 D3 D2 D1 D0
STBY
DISP
--
Register No.
(1) STBY 1: Standby function on 0: Normal (standby function off) Note: When standby function is on, all registers are reset to 0's. (2) DISP 1: LCD on 0: LCD off (3) Register No. Bit No. 0 1 2 3 4 5 2 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 0 1 0 1 Register Display memory X address register Y address register Control register Mode register C select register
(4) BUSY FLAG (can be read only) 1: Busy state 0: Ready state
Figure 27 Address Register
997
HD66108
2. Display Memory (DRAM) (Accessed with RS = 1, Register Number = (B'000) Although display memory (Figure 28) is not a register, it can be handled as one. 8- or 6-bit data can be selected by the control register WLS bit according to the character font in use. If 6-bit data is selected, D7 and D6 bits are invalid. 3. X Address Register (XAR) (Accessed with RS = 1, Register Number = (B'001) This register (Figure 29) contains 3 invalid bits (D7 to D5) and 5 valid bits (D4 to D0). It sets X addresses and confirms X addresses after writing or reading to or from the display memory. 4. Y Address Register (YAR) (Accessed with RS = 1, Register Number = (B'010) This register (Figure 30) contains 1 invalid bit (D7) and 7 valid bits (D6 to D0). It sets Y addresses and confirms Y addresses after writing or reading to or from the display memory.
D7 D6 D5 D4 D3 D2 D1 D0
8-bit data
*
*
6-bit data
Reading bits marked with * return 0s and writing them is invalid.
Figure 28 Display Memory
D7 D6 -- D5 D4 D3 D2 XAD D1 D0
XAD: 0 to 20 (H'00 to H'14) when display data is 8 bits long and 0 to 27 (H'00 to H'1B) when display data is 6 bits long. A maximum of H'1F is programmable.
Figure 29 X Address Register
D7 -- D6 D5 D4 D3 YAD D2 D1 D0
YAD: 0 to 64 (H'00 to H'40)
Figure 30 Y Address Register
998
HD66108
5. Control Register (FCR) (Accessed with RS = 1, Register Number = (B'011) This register (Figure 31), containing eight bits, has a variety of functions such as specifying the method for accessing RAM, determining RAM valid area, and selecting the function of the LCD driving signal output pins. It must be initialized as soon as possible after power-on since it determines the overall operation of the HD66108T. The PON bit may have to be reset afterwards. If the DUTY bits are rewritten after initialization at power-on (if values other than the initial values are desired), the display memory will not preserve data; the display memory must be set again after a time period of tCL1 or longer. For determining tCL1, refer to equation 1 (Section 3.1).
D7 INC D6 WLS D5 PON D4 ROS D3 D2 D1 DUTY D0
(1) INC (address increment direction select) 1: X address is incremented 0: Y address is incremented (2) WLS (word length (of display data) select) 1: 6-bit word 0: 8-bit word (3) PON (row data protect on) 1: Protect function on 0: Protect function off (4) ROS (row output (function of LCD driving output pins) select) Bit No. 0 1 2 3 4 0 0 1 1 3 0 1 0 1 Contents 165 column outputs 65 row outputs from the right side 65 row outputs from the left and right sides 33 row outputs from the right side
(5) DUTY (multiplexing duty ratio) Bit No. 0 1 2 3 4 5 6 7 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 Multiplexing Duty Ratio 1/32 1/34 1/36 1/48 1/50 1/64 1/66 Invalid (testing mode)
Figure 31 Control Register
999
HD66108
6. Mode Register (MDR) (Accessed with RS = 1, Register Number = (B'100) This register (Figure 32), containing 3 invalid bits (D7 to D5) and 5 valid bits (D4 to D0), selects a system clock and type of LCD driving waveform. It must also be initialized after power-on since it determines overall HD66108T operation like the FCR register. If the FFS bits are rewritten after initialization at power-on (if values other than the initial values are desired), the display memory will not preserve data; the display memory must be set again after a time period of tCL1 or longer. For determining tCL1, refer to equation 1 in section 3.1).
D7 D6 -- D5 D4 D3 FFS D2 D1 D0
DWS
(1) FFS (frame frequency select) Bit No. 0 1 2 3 4 5 6 7 4 0 0 0 0 1 1 1 1 3 0 0 1 1 0 0 1 1 2 0 1 0 1 0 1 0 1 FrequencyDivision Ratio 1 1/2 1/3 1/4 1/6 1/8 2 --
(2) DWS (LCD driving waveform select) Bit No. 0 1 2 3 1 0 0 1 1 0 0 1 0 1 Driving Waveform A-type waveform B-type waveform C-type waveform --
Figure 32 Mode Register
1000
HD66108
7. C Select Register (CSR) (Accessed with RS = 1, Register Number = (B'101) This register (Figure 33) contains 2 invalid bits (D7 and D6) and 5 valid bits (D5 to D0). It controls Ctype waveforms and is activated only when MDR register's DWS bits are set for this type of waveform.
D7 -- D6 D5 EOR D4 D3 D2 CLN D1 D0
(1) EOR (B-type waveform M signal + no. of counting lines on/off) 1: EOR function on 0: EOR function off (2) CLN (No. of counting lines in C-type waveform) 1 to 31 should be set in these bits; 0 must not be set.
Figure 33 C Select Register
1001
HD66108
Reset Function
The #$% pin starts the HD66108T after power-on. A #$% signal must be input via this pin for at least 20 s to prevent system failure due to excessive current created after power-on. Figure 34 shows the reset definition. (1) The Status of Pins during Reset Table 7 shows the reset status of output pins. The pins return to normal operation after reset. Table 7 The Status of Pins during Reset
Pin OSC2 CO CL1 FLM M Xn Xn' Status Outputs clock pulses or oscillates Outputs clock pulses Low (master chip) or high-impedance (slave chip) Low (master chip) or high-impedance (slave chip) Low (master chip) or high-impedance (slave chip) V4 (column output pins) V5 (row output pins)
RESET
0.15 x VCC At reset During reset (reset status)
0.15 x VCC After reset
Figure 34 Reset Definition
1002
HD66108
(2) The Status of Registers during Reset The #$% signal has no effect on registers or register bits except for the address register's STBY bit and the X and Y address registers, which are reset to 0's by the signal. Table 8 shows the reset status of registers. (3) Status after Reset The display memory does not preserve data which has been written to it before reset; it must be set again after reset. A #$% signal terminates the standby mode. Table 8
Register Address register X address register Y address register Control register Mode register C select register Display memory
The Status of Registers during Reset
Status Pre-reset status with the STBY bit reset to 0 Reset to 0's Reset to 0's Pre-reset status Pre-reset status Pre-reset status Preserves no pre-reset data
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HD66108
Precautionary Notes When Using the HD66108T (1) Install a 0.1-F bypass capacitor as close to the LSI as possible to reduce power supply impedance (VCC-GND and VCC-VEE). (2) Do not leave input pins open since the HD66108T is a CMOS LSI; refer to "Pin Functions" on how to deal with each pin. (3) When using the internal oscillation clock, attach an oscillation resistor as close to the LSI as possible to reduce coupling capacitance. (4) Make sure to input the reset signal at power-on so that internal units operate as specified. (5) Maintain the LCD driving power at VCC during standby state so that DC is not applied to an LCD, in which Xn pins are fixed at V4 or V5 level. Programming Restrictions (1) After busy time is terminated, an X or Y address is not incremented until 0.5-clock time has passed. If an X or Y address is read during this time period, non-updated data will be read. (The addresses are incremented even in this case.) In addition, the address increment direction should not be changed during this time since it will cause malfunctions. (2) Although the maximum output rows is 33 when 33-row-output mode from the right side is specified, any multiplexing duty ratio can be specified. Therefore, row output data sufficient to fill the specified duty must be input in the Y direction. Figure 35 shows how to set row data in the case of 1/34 multiplexing duty ratio. In this case, 0s must be set in Y33 since data for the 34th row (Y33) are not output. (3) Do not set the C select register's CLN bits to 0 for the M signal of C-type waveform.
X132 X131 X133 00 00 00 00 X164 X163 01 10 00 00
Y0 Y1 Y2 Y3
Y30 Y31 Y32 Y33
0 0 1 0
0 1 0 0
0 0 0 0
0 0 0 0
All 0's
Display data area
Row data area
Figure 35 How to Set Row Data for 33-Row Output from the Right Side
1004
HD66108
Absolute Maximum Ratings
Item Power supply voltage (1) Power supply voltage (2) Input voltage Operating temperature Storage temperature Symbol VCC1 to VCC3 VCC-VEE Vin Top Tstg Ratings -0.3 to +7.0 -0.3 to +16.5 -0.3 to VCC + 0.3 -20 to +75 -40 to +125 Unit V V V C C
Notes: 1. Permanent LSI damage may occur if the maximum ratings are exceeded. Normal operation should be under recommended operating conditions (VCC = 2.7 to 6.0V, GND = 0V, Ta = -20 to +75C). If these conditions are exceeded, LSI malfunctions could occur. 2. Power supply voltages are referenced to GND = 0V. Power supply voltage (2) indicates the difference between VCC and VEE.
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HD66108
Electrical Characteristics
DC Characteristics (1) (VCC = 5V 20%, GND = 0V, VCC - VEE = 6.0 to 15V, Ta = -20 to +75C, unless otherwise noted)
Item Input high voltage OSC1
0/S,
Symbol Min VIH1 0.8 x VCC 0.7 x VCC 0.85 x VCC 2.0 -0.3 -0.3 -0.3 -0.3 0.9 x VCC 2.4 -- -- -2.5
Typ -- -- -- -- -- -- -- -- -- -- -- -- --
Max VCC + 0.3 VCC + 0.3 VCC +0.3 VCC + 0.3 0.2 x VCC 0.3 x VCC
Unit Test Conditions V V V V V V VCC = 5V 10%
Note s
CL1, FLM, M, VIH2 TEST1, TEST2
5(6(7
VIH3 VIH4 VIL1
The other inputs Input low voltage OSC1
0/S,
5
CL1, FLM, M, VIL2 TEST1, TEST2
5(6(7
VIL3 VIL4 VOH1 VOH2 VOL1 VOL2 IIIL
0.15 x VCC V 0.8 -- -- 0.1 x VCC 0.4 2.5 V V V V V A VCC = 5V 10% -IOH = 0.1 mA -IOH = 0.2 mA VCC = 5V 10% IOL = 0.1 mA IOL = 1.6 mA VCC = 5V 10% Vin = 0 to VCC 8 7 6
The other inputs Output high voltage CO, CL1, FLM, M DB7-DB0 Output low voltage CO, CL1, FLM, M DB7-DB0 Input leakage current Tri-state leakage current V pins leakage current All except DB7-DB0, CL1, FLM, M DB7-DB0, CL1, FLM, M V1L, V1R, V3, V4, V6L, V6R, VMHn, VMLn
ITSL
-10
--
10
A
Vin = 0 to VCC
IVL
-10
--
10
A
Vin = VEE to VCC
Current During display consumption
ICC1 ICC2
-- -- --
-- -- --
400 1.0 10
A mA A
External clock fOSC = 500 kHz
1
Internal oscillation 1 Rf = 91 k 1, 2
During standby
ISB
1006
HD66108
Item ON resistance between Vi and Xj X0-X164 Symbol RON Min -- Typ -- Max 10 Unit k Test Conditions ILD = 50 A VCC-VEE = 10V Notes 3
V pins voltage range Oscillating frequency
AEV fOSC
-- 315
-- 450
35 585
% kHz Rf = 91 k
4
Notes: 1. When voltage applied to input pins is fixed to VCC or to GND and output pins have no load capacity. 2. When the LSI is not exposed to light and Ta = 0 to 40C with the STBY bit = 1. If using external clock pulses, input pins must be fixed high or low. Exposing the LSI to light increases current consumption. 3. ILD indicates the current supplied to one measured pin. 4. AEV = 0.35 x (VCC-VEE). For levels V1, V2, and V3, the voltage supplied should be between the VCC and the AEV and for levels V4, V5, and V6, the voltage supplied should be between the V EE and the AEV (Figure 36). 5. VIH4 (min) = 0.7 x VCC when used under conditions other than VCC = 5V 10%. 6. VIL4 (max) = 0.15 x VCC when used under conditions other than VCC = 5V 10%. 7. VOH2 (min) = 0.9 x VCC (-IOH = 0.1 mA) when used under conditions other than VCC = 5V 10%. 8. VOL2 (max) = 0.1 x VCC (IOL = 0.1 mA) when used under conditions other than VCC = 5V 10%.
1007
HD66108
DC Characteristics (2) (VCC = 2.7 to 4.0V, GND = 0V, VCC -VEE = 6.0 to 15V, Ta = -20 to +75C, unless otherwise noted)
Item Input high voltage Input low voltage
5(6(7
Symbol Min VIH1 VIL1 0.85 x VCC 0.7 x VCC -0.3
Typ Max -- -- -- VCC + 0.3 VCC + 0.3 0.3 x VCC
Unit Test Conditions V V V
Notes
The other inputs VIH2 OSC1, CL1, FLM, TEST1, TEST2, M
0S,
The other inputs VIL2 Output high voltage Output low voltage Input leakage current Tri-state leakage current V pins leakage current Current consumption All except DB7-DB0, CL1, FLM, M DB7-DB0, CL1, FLM, M V1L, V1R, V3, V4, V6L, V6R, VMHn, VMLn During display VOH1 VOL1 IIIL
-0.3 0.9 x VCC -- -2.5
-- -- -- --
0.15 x VCC -- 0.1 x VCC 2.5
V V V A -IOH = 50 A IOL = 50 A Vin = 0 to VCC
ITSL
-10
--
10
A
Vin = 0 to VCC
IVL
-10
--
10
A
Vin = VEE to VCC
ICC1 ICC2
-- -- -- --
-- -- -- --
260 700 10 10
A A A k
External clock fOSC = 500 kHz
1
Internal oscillation 1 Rf = 75 k 1, 2 ILD = 50 A VCC-VEE = 10V 3
During standby state ON resistance between Vi and Xj X0-X164
ISB RON
V pins voltage range Oscillating frequency
AEV fOSC
-- 315
--
35
% kHz Rf = 75 k
4
450 585
Notes: 1. When voltage applied to input pins is fixed to VCC or to GND and output pins have no load capacity. Exposing the LSI to light increases current consumption. 2. When the LSI is not exposed to light and Ta = 0 to 40C with the STBY bit = 1. If using external clock pulses, input pins must be fixed high or low. 3. ILD indicates the current supplied to one measured pin. 4. AEV = 0.35 x (VCC-VEE). For levels V1, V2, and V3, the voltage supplied should be between the VCC and the AEV and for levels V4, V5, and V6, the voltage supplied should be between the V EE and the AEV (Figure 36).
1008
HD66108
VCC V V1, V2, V3 levels
V VEE
V4, V5, V6 levels
Figure 36 Driver Output Waveform and Voltage Levels
1009
HD66108
AC Characteristics (1) (VCC = 4.5 to 6.0V, GND = 0V, Ta = -20 to +75C, unless otherwise noted) 1. CPU Bus Timing (Figure 37)
Item 5' high-level pulse width 5' low-level pulse width :5 high-level pulse width :5 low-level pulse width
:5-5' &6, &6,
Symbol tWRH tWRL tWWH tWWL tWWRH tAS tAH tDSW tDHW tDDR tDHR tCYC tWCH tWCL
Min 190 190 190 190 190 0 0 100 0 -- 20 0.25 0.1 0.1 --
Max -- -- -- -- -- -- -- -- -- 150 -- 5.0 -- -- 20
Unit ns ns ns ns ns ns ns ns ns ns ns s s s ns
high-level pulse width
RS setup time RS hold time Write data setup time Write data hold time Read data output delay time Read data hold time External clock cycle time External clock high-level pulse width External clock low-level pulse width
Note Note
External clock rise and fall time tr, tf Note: Measured by test circuit 1 (Figure 39).
2. LCD Interface Timing (Figure 38)
Item
0/S
= 0 CL1 High-level pulse width CL1 Low-level pulse width FLM Delay time FLM Hold time M output delay time
Symbol tWCH1 tWCL1 tDFL1 tHFL1 tDMO1 tWCH2 tWCL2 tDFL2
Min 35 35 -2.0 -2.0 -2.0 35 11 x tCYC -2.0
Max -- -- +2.0 +2.0 +2.0 -- -- 1.5 x tCYC
Unit s s s s s s s s
Notes 1, 4 1, 4 4 4 4 4 2, 4 3, 4
0/S
= 1 CL1 High-level pulse width CL1 Low-level pulse width FLM Delay time
FLM Hold time tHFL2 -2.0 +2.0 s 4 M delay time tDMI -2.0 +2.0 s 4 Notes: 1. When ROSC is 91 k (VCC = 4.0 to 6V) or 75 k (VCC = 2.0 to 4.0V) and bits FFS are set for 1. 2. When bits FFS are set for 1 or 2. The value is 19 x tCYC in other cases. 3. When bits FFS are set for 1 or 2. The value is 8.5 x tCYC in other cases. 4. Measured by test circuit 2 (Figure 39).
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HD66108
AC Characteristics (2) (VCC = 2.7 to 4.5V, GND = 0V, Ta = -20 to +75C, unless otherwise noted) 1. CPU Bus Timing (Figure 37)
Item 5' high-level pulse width 5' low-level pulse width :5 high-level pulse width :5low-level pulse width
:5-5' &6 &6
Symbol tWRH tWRL tWWH tWWL tWWRH tAS tAH tDSW tDHW tDDR tDHR tCYC tWCH tWCL
Min 1.0 1.0 1.0 1.0 1.0 0.5 0.1 1.0 0 -- 20 1.6 0.7 0.7 --
Max -- -- -- -- -- -- -- -- -- 0.5 -- 5.0 -- -- 0.1
Unit s s s s s s s s s s ns s s s s
high-level pulse width
RS setup time RS hold time Write data setup time Write data hold time Read data output delay time Read data hold time External clock cycle time External clock high-level pulse width External clock low-level pulse width
Note Note
External clock rise and fall time tr, tf Note: Measured by test circuit 2 (Figure 39).
2. LCD Interface Timing (Figure 38)
Item
0/S
= 0 CL1 High-level pulse width CL1 Low-level pulse width FLM Delay time FLM Hold time M output delay time
Symbol tWCH1 tWCL1 tDFL1 tHFL1 tDMO1 tWCH2 tWCL2 tDFL2
Min 35 35 -2.0 -2.0 -2.0 35 11 x tCYC -2.0
Max -- -- +2.0 +2.0 +2.0 -- -- 1.5 x tCYC
Unit s s s s s s s s
Notes 1, 4 1, 4 4 4 4 4 2, 4 3, 4
0/S
= 1 CL1 High-level pulse width CL1 Low-level pulse width FLM Delay time
FLM Hold time tHFL2 -2.0 +2.0 s 4 M delay time tDMI -2.0 +2.0 s 4 Notes: 1. When ROSC is 91 k (VCC = 4.0 to 6V) or 75 k (VCC = 2.7 to 4.0V) and bits FFS are set for 1. 2. When bits FFS are set for 1 or 2. The value is 19 x tCYC in other cases. 3. When bits FFS are set for 1 or 2. The value is 8.5 x tCYC in other cases. 4. Measured by test circuit 2 (Figure 39).
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HD66108
CS RS VIH VIL tAS WR VIH VIL tWWRH tWRH RD VIH VIL tDSW VIH DB0-DB7 VIL tDHW tDDR VOH VOL tDHR tWRL tWWL tAH tAS tAH
tWWH
Figure 37 CPU Bus Timing
tWCH1/tWCH2 VOH/VIH CL1 VOH/VIL tDFL1/tDFL2 VOH/VIL FLM VOL/VIL tDMO/tDMI VOH/VIH VOL/VIL tHFL1/tHFL2 tWCL1/tWCL2
M
Figure 38 LCD Interface Timing
1012
HD66108
5.0V
RL
C
R All diodes are IS2074 H
RL = 2.4 k R = 11 k C = 130 pF Test Circuit 1
C
C = 50 pF Test Circuit 2
Figure 39 Load Circuits
1013

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